Method of fabricating semiconductor optical device

ABSTRACT

In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure are formed on a primary surface of a first group III-V semiconductor region. After forming the insulating structures, a second group III-V semiconductor region is grown on the first group III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second group III-V semiconductor region. After forming the second group III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to an electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a semiconductoroptical device.

2. Related Background Art

Publication 1 (Japanese Patent Application Laid Open No. H10-64781)discloses a method of making an alignment mark on a substrate. In thismethod, a part of the semiconductor is etched to form a pattern forforming the alignment mark. A semiconductor crystal is selectively grownon the pattern to form the alignment mark. Semiconductor films differingin thickness and composition are deposited on the same substrate in theselective growth of semiconductor for making a semiconductor integratedoptical device, and this method provides the easy formation of alignmentmarks which facilitate the alignment.

SUMMARY OF THE INVENTION

When alignment marks are formed by wet-etching a part of the surface ofa compound semiconductor substrate, electron beam exposure apparatusescannot detect them very well. When alignment marks are formed bydry-etching a part of the surface of a compound semiconductor substrate,this process may degrade the reliability of the semiconductor opticaldevices and this degradation should be avoided in order to obtain thegood reliability thereof.

It is an object to provide a method of fabricating a semiconductoroptical device, and this method provides an excellent alignment in thestep of the direct writing of a pattern for a diffraction grating of thesemiconductor optical device by use of electron beam exposureapparatuses.

One aspect of the present invention is a method of fabricating asemiconductor optical device. The method comprises the steps of: forminginsulating structures for an alignment mark for use in electron beamexposure on a primary surface of a first group III-V semiconductorregion; after forming the insulating structures, growing a second groupIII-V semiconductor region on the first group III-V semiconductor regionto form an epitaxial wafer; after growing the second group III-Vsemiconductor region, performing alignment for the electron beamexposure; and after the alignment, exposing a resist to an electron beamto form a resist mask having a pattern for a diffraction grating. Theresist is provided on the epitaxial wafer. The height of the insulatingstructures is larger than thickness of the second group III-Vsemiconductor region.

In the method according to the present invention, the method furthercomprises the step of, after growing the second group III-Vsemiconductor region and prior to the alignment, forming depressing inthe second group III-V semiconductor region by removing the insulatingstructures.

In the method according to the present invention, the alignment in theelectron beam exposure may be performed by use of these depressions.Steps are provided by the edges of the depressions.

In the method according to the present invention, the alignment in theelectron beam exposure may be performed without removing the insulatingstructures. Steps are provided by the edges of the insulatingstructures.

In the method according to the present invention, each of the insulatingstructures has a post-like shape and has a side extending in a directionintersecting with the primary surface of the first group III-Vsemiconductor region.

In the method according to the present invention, the method furthercomprises the steps of: depositing an insulating layer on the firstgroup III-V semiconductor region; and etching the insulating layer toform the insulating structures.

In the method according to the present invention, the insulatingstructures may be arranged to form the alignment mark.

In the method according to the present invention, the insulating layermay be formed in a single deposition step. Alternatively, the insulatinglayer may be formed by depositing a number of insulating films.

In the method according to the present invention, the insulating layermay be formed by induction-coupled plasma method. In the methodaccording to the present invention, the thickness of the insulatinglayer may be equal to or more than two micrometers.

In the method according to the present invention, the method furthercomprises the steps of: etching the second group III-V semiconductorregion by use of the resist mask to form a periodic structure for thediffraction grating in the second group III-V semiconductor region; andforming a third group III-V semiconductor region over the periodicstructure of the second group III-V semiconductor region. In the methodaccording to the present invention, the third group III-V semiconductorregion may include an active layer.

In the method according to the present invention, the second group III-Vsemiconductor region may include an active layer. Alternatively, in themethod according to the present invention, the third group III-Vsemiconductor region may include an active layer.

In the method according to the present invention, the insulating layermay be made of silicon inorganic compound. In the method according tothe present invention, the silicon inorganic compound may be siliconoxide.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and other objects, features, and advantages of thepresent invention will be understood easily from the following detaileddescription of the preferred embodiments of the present invention withreference to the accompanying drawings.

FIG. 1 is a schematic view showing cross sections of substrate productsin primary steps in the method of fabricating a semiconductor opticaldevice according to the present invention.

FIG. 2 is a schematic view showing cross sections of substrate productsin primary steps in the method of fabricating the semiconductor opticaldevice.

FIG. 3 is a schematic view showing top surfaces of substrate products inprimary steps in the method of fabricating the semiconductor opticaldevice.

FIG. 4 is a schematic top view showing top surfaces of substrateproducts in primary steps in the method of fabricating the semiconductoroptical device.

FIG. 5 is a schematic view showing cross sections of substrate productsin primary steps in the method of fabricating the semiconductor opticaldevice.

FIG. 6 is a schematic view showing top surfaces of substrate products inprimary steps in the method of fabricating the semiconductor opticaldevice.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The teaching of the present invention will readily be understood in viewof the following detailed description with reference to the accompanyingdrawings illustrated by way of example. Referring to the accompanyingdrawings, embodiments of a method of fabricating a semiconductor opticaldevice of the present invention will be explained. When possible, partsidentical to each other will be referred to with symbols identical toeach other.

FIGS. 1 to 6 are schematic views explaining primary steps in the methodof fabricating a semiconductor optical device. In the following, themethod of fabricating a distributed feedback (DBF) semiconductor laserwill be explained as an example of the semiconductor optical device.

As shown in part (a) of FIG. 1, a substrate, such as InP substrate 11,is prepared, and semiconductor layers are grown thereon. The InPsubstrate 11 is one of available group III-V compound semiconductorsubstrates, and provides a group III-V compound semiconductor regionused as a base on which semiconductor layers are deposited. In thesubsequent explanation, the InP substrate 11 is referred to as thesubstrate, but the substrate available for the present invention is notlimited thereto. Other semiconductor substrates, such as GaAs substrateand GaN substrate, can be used as the substrate.

As shown in part (b) of FIG. 1, an insulating layer 13 is formed on theprimary surface 11 a of the InP substrate 11. The thickness of theinsulating layer 13 is larger than that of the group III-V compoundsemiconductor region, for example semiconductor layers, that is made inthe following step, and in a preferred example, the insulating layer 13can be made of silicon inorganic compound, aluminum inorganic compoundand so on. The silicon inorganic compound can be silicon compoundincluding at least one of oxygen and nitrogen, such as silicon oxide(for example, SiO.sub.2) and silicon nitride (for example, SiN). Thealuminum inorganic compound can be aluminum oxide (for example,Al.sub.2O.sub.3). When the insulating layer 13 is made of silicon oxide,it is preferable to use a silicon oxide film formed by induction coupledplasma chemical vapor deposition (ICP-CVD) method. The ICP-CVD methodpermits the formation of low-stressed silicon oxide layers and thus canprovide a thick silicon oxide layer which can be used for the insulatinglayer 13. Further, it is advantageous that the insulating layer 13 of alow-stressed silicon oxide layer formed on a substrate reduces thestress that is applied to the substrate. Furthermore, the insulatinglayer 13 can be made of a thick single film, thereby avoiding therepetition of film formations

An example of the growth recipes of ICP-CVD is as follows:

Gas for depositing film: Tetra Ethyl Ortho Silicate (TEOS)

Flow rate of TEOS: 10 sccm

Flow rate of O₂: 100 sccm

RF power for generating plasma: 1000 watts

RF power for adjusting refractive index: 0 to 300 watts

Pressure: 5 Pa

Substrate temperature: 400 degrees Celsius or lower

Deposition rate: 300 nm/min.

The ICP-CVD method permits the formation of SiO₂ films of thickness upto about 5 micrometers.

For example, when the thickness of the insulating layer 13 is equal toor more than two micrometers, the top of the insulating layer 13 ishigher than the top surface of the semiconductor layers that is grown inthe subsequent growth step.

As shown in part (c) of FIG. 1, a mask 17 is formed on the insulatinglayer 13. The mask 17 has the pattern that is transferred to a mark foruse in alignment in electron beam exposure (hereinafter referred to as“EB exposure”) of the subsequent steps. The mask 17 is made of, forexample, resist, and is patterned by photolithography.

As shown in part (a) of FIG. 2, the insulating layer 13 is etched usingthe mask 17. This etching may be dry etching, for example, andselectively remove a part of the insulating layer 13 to form a number ofinsulating structures 19 provided on the primary surface of thesubstrate 11. Each of the insulating structures 19 has a shapepreferable for the alignment in the EB exposure step. For example, theinsulating structures 19 are arranged at the reference position foralignment in the EB exposure step, and are shaped like a post, forexample.

As shown in part (b) of FIG. 2, a group III-V compound semiconductorregion is formed on the primary surface 11 a of the substrate 11 afterforming the insulating structures 19. In the present example, the groupIII-V compound semiconductor region can be a laminated region 21. Thelaminated region 21 has a side 21 a, and the side 21 a is in contactwith the side of each of the insulating structures 19. The laminatedregion 21 includes a number of group III-V compound semiconductor layers23, 25, 27 and 29, and these layers 23, 25, 27 and 29 are sequentiallystacked on the substrate 11. It is preferable that these group III-Vcompound semiconductor layers 23, 25, 27 and 29 be grown bymetal-organic-vapor-phase epitaxy (MOVPE). The group III-V compoundsemiconductor layers 23, 25, 27 and 29 are selectively grown on thesubstrate, and are not grown on the surface of the insulating mask. Thegroup III-V compound semiconductor layer 23 is provided for a firstconductive type cladding layer, and the first conductive type claddinglayer is made of, for example, n-type InP. The group III-V compoundsemiconductor layer 25 is provided for a first optical guide layer, andthe first optical guide layer is made of, for example, n-type GaInAsP.The group III-V compound semiconductor layer 27 is provided for anactive layer of the semiconductor optical device, and the structure ofthe active layer may be a bulk, single quantum well or multiple quantumwell. The group III-V compound semiconductor layer 29 is provided for asecond optical guide layer, and the second optical guide layer is madeof, for example, p-type GaInAsP. In the present embodiment, crystalgrowth for the active layer is carried out before the EB exposure step,and the diffraction grating is formed on the second optical guide layer.

If required, as shown in part (c) of FIG. 2, the insulating structures19 may be removed, and wet etching can be used for this removal. Whenthe insulating structures 19 are made of silicon oxide, the siliconoxide insulating structures can be selectively removed by hydrofluoricacid and so on, and the laminated region 21 made of group III-V compoundsemiconductor is not removed thereby. The insulating structures 19 areformed before depositing the laminated region 21, and after depositingthe laminated region 21, the insulating structures 19 are removed toform an epitaxial wafer E1. The laminated region 21 in the epitaxialwafer E1 is provided with a number of depressions formed by the removalof the insulating structures 19 without etching semiconductor. Theformation and removal of the insulating structures 19 permits theformation of the steps 33 that are located at the edges of depressions31. The steps 33 are independent of crystal orientation of the laminatedregion 21. The epitaxial wafer E1 includes the depressions 31, e.g.,empty holes, in the laminated region 21. Each of the depressions 31 hasa side 21 a, and the side 21 a extends in a direction intersecting withthe top surface of the laminated region 21. The side has steep edges,and for example, the side is approximately perpendicular to the topsurface of the laminated region 21.

After forming the laminated region 21, alignment in the EB exposure stepis performed. Prior to the alignment, as shown in part (a) of FIG. 3,resist is applied onto the surface of the laminated region 21 to form aresist film 32. The alignment of EB exposure is performed by use of thesteps 33 (depressions 31). Two squares are drawn in part (a) of FIG. 3to show the steps 33 (depressions 31) as a representative example.

In the above steps, since the height of the insulating structures 19 isgreater than the thickness of the laminated region 21, the selectiveremoval of the insulating structures 19 with respect to the laminatedregion 21 can be performed even after the laminated region 21 has beenformed. The empty holes formed by the above selective removal can beused as alignment marks for the alignment of EB exposure. Therefore, asshown in part (b) of FIG. 3, the appropriate alignment can be performedby using the depressions 31 as alignment marks, and a mask 35 made ofresist is formed on the epitaxial wafer E1 by EB exposure anddevelopment. The mask 35 has patterns 35 a, 35 b and 35 c for adiffraction grating, for example.

As shown in part (c) of FIG. 3, the laminated region 21 is etched usingthe patterned mask 35. After this etching, the mask 35 is removed. Afterthe etching and removal, periodic structures 37 a, 37 b and 37 c for thediffraction grating is formed in the laminated region 21.

As shown in part (a) of FIG. 4, a group III-V compound semiconductor 39is grown so as to cover the structures 37 a, 37 b and 37 c. In thisstep, diffraction gratings 41 a, 41 b and 41 chave formed using the mask35 patterned by the appropriate alignment. The group III-V compoundsemiconductor 39 can be a second conductive type cladding layer, and thesecond conductive type cladding layer is made of, for example, p-typeInP. A group III-V compound semiconductor 40 is grown on the group III-Vcompound semiconductor 39. The group III-V compound semiconductor 40 canbe a second conductive type capping layer, and the second conductivetype capping layer is made of, for example, p-type GaInAs.

Next, as shown in part (b) of FIG. 4, mesa waveguide structures 43 a, 43b and 43 c are formed, and each of the mesa waveguide structures 43 a,43 b and 43 c includes the part of the laminated region 21 and groupIII-V compound semiconductors 39, 40. An insulating film of siliconoxide or silicon nitride is formed onto the group III-V compoundsemiconductor 40. The insulating film is made of silicon oxide orsilicon nitride such as SiO.sub.2 or SiN, for example, and the siliconoxide and silicon nitride can be formed by plasma chemical vapordeposition (CVD) method. Silane and oxygen can be used as source gas forforming the silicon oxide, and silane and nitrogen can be used as sourcegas for forming the silicon nitride. The thickness of the insulatingfilm is about 0.1 micrometers. Then, resist is applied onto theinsulating film. After the application of the resist, a pattern of amask for forming the mesa waveguide structures 43 a, 43 b and 43 c istransferred to the resist. The pattern that is the same as that of theresist mask for forming the mesa waveguide structures 43 a, 43 b and 43c is transferred to the insulating film by using the resist as the mask.Then, the resist is removed. As shown in part (a) of FIG. 5, a mask 42made of the insulating film is formed on the group III-V compoundsemiconductor 40. Since the pattern for forming the mesa waveguidestructures 43 a, 43 b and 43 c should be positioned to the diffractiongratings 41 a, 41 b and 41 c, the alignment in the patterning step canbe performed by use of the steps 33 again. As shown in part (b) of FIG.5, the mesa waveguide structures 43 a, 43 b and 43 c are formed by wetetching using the mask 42 of insulating material. The etchant ofBr-methanol can be used in this wet etching process. Each of the mesawaveguide structures 43 a, 43 b and 43c includes the diffractiongratings 41 a, 41 b and 41 c and the part of the semiconductor laminatedregion 21 containing the active layer. Alternatively, before the abovewet etching process, an insulating layer may be formed on alignment maskareas in the laminated region 21 to cover the surfaces of the alignmentmarks. In the wet etching process, the depressions 31 in the alignmentmask areas are not etched, and remain unchanged.

As shown in part (c) of FIG. 4, a burying layer 45 is selectively grownon the substrate 11 by MOVPE, and the burying layer 45 cover the sidesof the mesa waveguide structures 43 a, 43 b and 43 c. The burying layer45 is not grown on the insulating film located on the mesa waveguidestructures 43 a, 43 b and 43 c. For example, InP semiconductor is formedin this burying regrowth step. As shown in part (c) of FIG. 5, theburying layer 45 includes p-type InP layer 45 a and n-type Inp layer 45b. After the burying regrowth, another second conductive typesemiconductor cladding layer 47 and a second conductive typesemiconductor contact layer 49 are grown by MOVPE on the substrate 11.These layers 47 and 49 are formed on the mesa waveguide structures 43 a,43 b and 43 c and the burying layer 45. The second conductive typesemiconductor cladding layer 47 is made of, for example, p-type InP, andthe second conductive type semiconductor contact layer 49 is made of,for example, p-type GaInAs.

Referring to part (c) of FIG. 4 again, an insulating film 51 is formedon the second conductive type semiconductor contact layer 49. Theinsulating film 51 is made of, for example, silicon oxide, and siliconoxide can be formed by plasma CVD method. The thickness of theinsulating film 51 is about 0.1 micrometers.

As shown in part (a) of FIG. 6, windows 53 a, 53 b, 53 c are formed inthe insulating film 51, and the top surface of the second conductivetype semiconductor contact layer 49 is exposed in the windows 53 a, 53b, 53 c. The alignment to form the windows 53 a, 53 b, 53 c can beperformed by use of the steps 33 such that the windows 53 a, 53 b, 53 care located on the mesa waveguide structures 43 a, 43 b and 43 c,respectively.

Next, as shown in part (b) of FIG. 6, first electrodes 55 a, 55 b, 55 care formed so as to cover the windows 53 a, 53 b, 53 c, respectively.These first electrodes 55 a, 55 b, 55 c, are provided for, for example,the anode electrodes of semiconductor lasers.

After backgrinding the substrate 11 to reduce its thickness to a desiredvalue, as shown in part (c) of FIG. 6, a second electrode 57 is formedon the backside of the processed substrate. The second electrode 57 isprovided for, for example, the cathode electrode of the DFBsemiconductor laser.

In the present embodiment described above, the insulating structures 19are removed to form depressions 31, e.g. holes, in the laminated region21. In a modified embodiment according to the present invention, thealignment of EB exposure is performed without removing the insulatingstructures 19. Although the laminated region 21 is formed after formingthe insulating structures 19, the laminated region 21 is not grown onthe insulating structures 19 and the steps are provided by the edges ofthe insulating structures 19. Since the height of the insulatingstructures 19 is greater than the thickness of the laminated region 21,the insulating structures 19 protruding from the laminated region 21 canbe also used as alignment marks for use in EB exposure, and provides theexcellent accuracy of the alignment for EB exposure. This method can beused to form a resist mask of a pattern for diffraction gratings. By useof this EB exposure method, the array of the diffraction gratings isalso formed on the epitaxial wafer.

In the above embodiments, the diffraction gratings are formed aftergrowing the active layer, but the diffraction gratings may be formedbefore growing the active layer.

As explained above, the method in the above embodiment Permits theformation of the alignment mark that can provides the easy detection andaccurate alignment in the EB exposure step.

Having described and illustrated the principle of the invention in apreferred embodiment thereof, it is appreciated by those having skill inthe art that the invention can be modified in arrangement and detailwithout departing from such principles. For example, the InP-basedburied DFB semiconductor laser having a one-dimensional diffractiongrating, but the application of present invention is not limited to thespecific examples disclosed in the embodiment. The present invention isapplicable to methods of making electronic devices, such as other typeDFB lasers and distributed reflector (DR) lasers, using EB exposure.Further, the insulating layer is formed in the single deposition in theembodiments, but a number of thin insulating films can be repeatedlydeposited to form the insulating layer. Details of devices and steps ofthe method can be modified as necessary. We therefore claim allmodifications and variations coming within the spirit and scope of thefollowing claims.

1. A method of fabricating a semiconductor optical device, the methodcomprising the steps of: forming insulating structures for an alignmentmark for use in electron beam exposure on a primary surface of a firstgroup III-V semiconductor region; after forming the insulatingstructures, growing a second group III-V semiconductor region on thefirst group III-V semiconductor region to form an epitaxial wafer, aheight of the insulating structures being larger than a thickness of thesecond group III-V semiconductor region; after growing the second groupIII-V semiconductor region, performing alignment in the electron beamexposure; and after the alignment, exposing a resist to an electron beamto form a resist mask having a pattern for a diffraction grating, theresist being provided on the epitaxial wafer.
 2. The method according toclaim 1, the method further comprising the step of, after growing thesecond group III-V semiconductor region and prior to the alignment,forming depressions in the second group III-V semiconductor region byremoving the insulating structures.
 3. The method according to claim 2,wherein the alignment in the electron beam exposure is performed by useof the depressions.
 4. The method according to claim 1, wherein thealignment in the electron beam exposure is performed without removingthe insulating structures.
 5. The method according to claim 1, whereineach of the insulating structures has a side, and the side extends in adirection intersecting with the primary surface of the first group III-Vsemiconductor region.
 6. The method according to claim 1, wherein thesecond group III-V semiconductor region includes an active layer.
 7. Themethod according to claim 2, wherein the second group III-Vsemiconductor region includes an active layer.
 8. The method accordingto claim 4, wherein the second group II-V semiconductor region includesan active layer.
 9. The method according to claim 1, the method furthercomprising the steps of: depositing an insulating layer on the firstgroup III-V semiconductor region; and etching the insulating layer toform the insulating structures.
 10. The method according to claim 9,wherein the insulating layer is formed in a single deposition step. 11.The method according to claim 9, wherein the insulating layer is formingby depositing a number of insulating films.
 12. The method according toclaim 9, wherein the insulating layer is formed by induction-coupledplasma method.
 13. The method according to claim 12, wherein thicknessof the insulating layer is equal to or more than two micrometers. 14.The method according to claim 1, the method further comprising the stepsof: etching the second group III-V semiconductor region by use of theresist mask to form a periodic structure for the diffraction grating inthe second group III-V semiconductor region; and forming a third groupIII-V semiconductor region over the periodic structure of the secondgroup III-V semiconductor region.
 15. The method according to claim 2,the method further comprising the steps of: etching the second groupIII-V semiconductor region by use of the resist mask to form a periodicstructure for the diffraction grating in the second group III-Vsemiconductor region; and forming a third group III-V semiconductorregion over the periodic structure of the second group III-Vsemiconductor region.
 16. The method according to claim 4, the methodfurther comprising the steps of: etching the second group III-Vsemiconductor region by use of the resist mask to form a periodicstructure for the diffraction grating in the second group III-Vsemiconductor region; and forming a third group III-V semiconductorregion over the periodic structure of the second group III-Vsemiconductor region.
 17. The method according to claim 14, wherein thethird group III-V semiconductor region includes an active layer.
 18. Themethod according to claim 2, wherein the depressions are arranged toform the alignment mark.
 19. The method according to claim 4, whereinthe insulating structures are arranged to form the alignment mark. 20.The method according to claim 1, wherein the insulating layer is made ofsilicon oxide.